FORMALIZED DEVELOPMENT FLOW FOR A CRYPTOGRAPHIC CONTROLLER WITH DIGITAL SIGNATURE AND FPGA-BASED VERIFICATION

This article presents and experimentally validates a formalized development flow for a specialized cryptographic controller designed for hardware implementation of digital signature algorithms. The flow covers the complete design cycle, encompassing architectural synthesis, RTL implementation, FPGA-based hardware verification, and physical implementation within an MPW flow. The controller architecture follows a modular design principle, in which the system is decomposed into functionally independent hardware blocks that are developed and verified individually. For each block, RTL implementation, software interface generation, and hardware verification are carried out during FPGA prototyping, enabling early detection of functional and interface errors. Critical components undergo additional physical verification through an RTLto-GDS flow, including DRC and LVS checks. Upon completion of modular verification, the blocks are integrated, a memory map is generated, and system-level hardware verification is performed. The approach was experimentally validated on a demonstration computing module based on the TinyQV (RISC-V) core, using the GOWIN Tang Primer 20K and TinyTapeout (PDK SkyWater SKY130) platforms. The results confirm the reproducibility of the proposed flow and its practical applicability for developing specialized cryptographic controllers and secure embedded systems.

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