kaz44Вестник Университета Шакарима. Серия технические наукиBulletin of Shakarim University. Technical Sciences2788-79953006-0524«Шәкәрім университеті» КеАҚ10.53360/2788-7995-2026-2(22)-2kaz44-2646Research ArticleАВТОМАТИЗАЦИЯ И ИНФОРМАЦИОННЫЕ ТЕХНОЛОГИИФОРМАЛИЗОВАННЫЙ МАРШРУТ РАЗРАБОТКИ КРИПТОГРАФИЧЕСКОГО КОНТРОЛЛЕРА ЭЛЕКТРОННОЙ ЦИФРОВОЙ ПОДПИСИ С ПЛИС-ВЕРИФИКАЦИЕЙFORMALIZED DEVELOPMENT FLOW FOR A CRYPTOGRAPHIC CONTROLLER WITH DIGITAL SIGNATURE AND FPGA-BASED VERIFICATIONhttps://orcid.org/0009-0008-4479-4478СенюшинИ. А.SeniushinI.

Игорь Анатольевич Сенюшин – проектный менеджер, 

010000, г. Астана, проспект Кабанбай Батыра, 51/1

Igor Seniushin – Project Manager, 

Astana, 51/1 Kabanbai Batyr Avenue

sigor@cybersec.kzhttps://orcid.org/0000-0002-0259-774XГлазыринаН. С.GlazyrinaN.

Наталья Сергеевна Глазырина – PhD, ассоциированный профессор, координатор научный проектов, 

010000, г. Астана, проспект Кабанбай Батыра, 51/1

Natalya Glazyrina – PhD, associate professor, scientific project coordinator, 

Astana, 51/1 Kabanbai Batyr Avenue

glazirinan@yandex.ruhttps://orcid.org/0000-0002-7800-9035ИбраевР. Б.IbrayevR.

Ренат Булатович Ибраев – специалист по криптографической безопасности, 

010000, г. Астана, проспект Кабанбай Батыра, 51/1

Renat Ibrayev – Cryptographic Security Specialist,

Astana, 51/1 Kabanbai Batyr Avenue

crypto.teacher2020@gmail.comhttps://orcid.org/0009-0003-2797-1421ДжилкибаевЕ. К.JilkibayevY.

Ерболсын Кайратович Джилкибаев – руководитель отдела разработки, 

010000, г. Астана, проспект Кабанбай Батыра, 51/1

Yerbolsyn Jilkibayev – Head of Development Department, 

Astana, 51/1 Kabanbai Batyr Avenue

yerbolsyn@proton.mehttps://orcid.org/0009-0000-1196-7952ӘділғазыұлыА.AdilgazyulyA.

Алмас Әділғазыұлы – студент школы инженерии и цифровых наук, 

010000, г. Астана, проспект Кабанбай Батыра, 53

Almas Adilgazyuly – Student, School of Engineering and Digital Sciences, 

Astana, 53 Kabanbai Batyr Avenue

almas.adilgazyuly@nu.edu.kzТОО «TSARKA R&D»КазахстанTSARKA R&D LLPKazakhstanНазарбаев УниверситетКазахстанNazarbayev UniversityKazakhstan20262907202602(22)1929Copyright © Сенюшин И.А., Глазырина Н.С., Ибраев Р.Б., Джилкибаев Е.К., Әділғазыұлы А., 20262026Сенюшин И.А., Глазырина Н.С., Ибраев Р.Б., Джилкибаев Е.К., Әділғазыұлы А.Seniushin I., Glazyrina N., Ibrayev R., Jilkibayev Y., Adilgazyuly A.Данная работа распространяется под лицензией Creative Commons Attribution 4.0.This work is licensed under a Creative Commons Attribution 4.0 License.https://tech.vestnik.shakarim.kz/jour/article/view/2646

В статье представлен и экспериментально апробирован формализованный маршрут разработки специализированного криптографического контроллера для аппаратной реализации алгоритмов электронной цифровой подписи. Разработанный маршрут охватывает полный цикл проектирования и включает этапы архитектурного синтеза, RTL-реализации, аппаратной верификации на ПЛИС и физической реализации в рамках MPW-потока. Архитектура контроллера построена по модульному принципу, при котором система представляет собой совокупность функционально независимых аппаратных блоков, разрабатываемых и верифицируемых как отдельные модули. Для каждого блока выполняются RTL-реализация, формирование программного интерфейса и аппаратная верификация на этапе ПЛИСпрототипирования, что обеспечивает раннее выявление функциональных и интерфейсных ошибок. Для критически важных компонентов дополнительно применяется физическая верификация в маршруте RTL-to-GDS с прохождением проектных проверок, включая DRC и LVS. После завершения модульной верификации выполняется интеграция блоков, формируется карта памяти и проводится системная аппаратная верификация. Экспериментальная апробация выполнена на демонстрационном вычислительном модуле на базе ядра TinyQV (RISC-V) с использованием платформ GOWIN Tang Primer 20K и TinyTapeout (PDK SkyWater SKY130). Полученные результаты подтверждают воспроизводимость предложенного маршрута и его практическую применимость для разработки специализированных криптографических контроллеров и защищённых встраиваемых систем.

This article presents and experimentally validates a formalized development flow for a specialized cryptographic controller designed for hardware implementation of digital signature algorithms. The flow covers the complete design cycle, encompassing architectural synthesis, RTL implementation, FPGA-based hardware verification, and physical implementation within an MPW flow. The controller architecture follows a modular design principle, in which the system is decomposed into functionally independent hardware blocks that are developed and verified individually. For each block, RTL implementation, software interface generation, and hardware verification are carried out during FPGA prototyping, enabling early detection of functional and interface errors. Critical components undergo additional physical verification through an RTLto-GDS flow, including DRC and LVS checks. Upon completion of modular verification, the blocks are integrated, a memory map is generated, and system-level hardware verification is performed. The approach was experimentally validated on a demonstration computing module based on the TinyQV (RISC-V) core, using the GOWIN Tang Primer 20K and TinyTapeout (PDK SkyWater SKY130) platforms. The results confirm the reproducibility of the proposed flow and its practical applicability for developing specialized cryptographic controllers and secure embedded systems.

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The authors declare that there are no conflicts of interest present.