POST-QUANTUM CRYPTOGRAPHY SABER IN A HYBRID CPU–FPGA ARCHITECTURE

The paper presents the development and optimization of a hybrid hardware-software implementation of the post-quantum cryptographic algorithm Saber on an embedded CPU-FPGA platform. The main objective of the research is to enhance the performance, energy efficiency, and security of post-quantum key exchange schemes under limited computational resources while maintaining resistance to side-channel attacks.
The proposed architecture integrates the computational capabilities of the ARM processor and the FPGA core, enabling efficient distribution of workloads between the processor and the hardware accelerator.
The hardware part implements pipelined polynomial multiplication and SHA-3 hashing, while the software component manages data flow, synchronization, and integrity control. A fixed-latency communication interface between the CPU and FPGA ensures constant-time execution and stability against timing variations.
Three implementations of the algorithm were compared: software, hardware, and hybrid. Experimental results demonstrated a 35-50% reduction in execution time without compromising cryptographic strength or increasing power consumption. A TVLA (Test Vector Leakage Assessment) analysis confirmed the absence of any statistical correlation between the energy profile and secret data, validating the system’s side-channel resistance.
The proposed solution can be effectively applied to mobile robotic platforms, unmanned marine vehicles, industrial telemetry networks, and IoT systems requiring high-performance and quantum-resistant data protection.

1. Jan-Pieter D’Anvers А. Vercauteren. Saber: Module-LWR Based Key Exchange / Jan-Pieter D’Anvers A., Karmakar S., Sinha Roy F. // CPA-Secure Encryption and CCA-Secure KEM. Springer, 2018.

2. Sinha Roy S. High-Speed Coprocessor for Lattice-Based Key Encapsulation Mechanism: Saber in Hardware / S. Sinha Roy, A. Basso // TCHES, 2020.

3. High-Performance Hardware Implementation of the Saber Key Encapsulation Protocol / D. Li et al // Electronics, 2024.

4. Dang V.B. High-Speed Hardware Architectures and FPGA Benchmarking of Kyber, NTRU, and Saber / V.B. Dang, K. Mohajerani, K. Gaj. // IEEE Trans. Computers, 2022.

5. Compact Co-Processor for Accelerating Module Lattice-Based KEM / J.M.B. Mera et al // IEEE, 2020.

6. Enhancing Cryptographic Protection and Authentication in Cellular Networks / M. Bakyt et al // IJECE, 2024.

7. Energy-Efficient Configurable Crypto-Processor for Module-LWR / Y. Zhu et al // IEEE Trans. Circuits and Systems I, 2021.

8. Abdulgadir A. First-Order Masked Implementation of Saber on FPGA / A. Abdulgadir, S. Sinha Roy, F. Vercauteren. // CHES, 2021.

9. Aikata C.M. Unified Saber and Dilithium Coprocessor for Post-Quantum Cryptography / C.M. Aikata, F. Turan, M. Knežević. // IEEE Access, 2022.

10. Dang V.B. FPGA Benchmarking of Lattice-Based KEMs: Kyber, Saber, and NTRU Prime / V.B. Dang, K. Gaj. // IEEE Trans. Computers, 2023.

11. D’Anvers J.-P. Specification of the Saber Algorithm / J.-P. D’Anvers, R. Vercauteren. // NIST PQC Round 3 Submission, 2020.

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